TOF (Timer Off) Ladder Logic Instruction

Description

The Timer Off instruction is a non-retentive timer that is enabled when the preceding logic is false. The timer is reset when the preceding logic is true. The timer can be compared to a stop watch. A value is entered into the preset and an accumulator keeps track of the time. When the accumulator reaches the preset, the timer-done bit is cleared. The timer-timing bit is set while the accumulator is active. When the preceding logic is true the accumulator is set to 0 and the EN and DN bit are set and the TT bit is cleared.

List of arguments

TIMER STRUCTURE          PRE DEFINED STRUCTURE

Tag Structure

  • BOOL     Timer.EN             Enable Bit, set when instruction is enabled (The TOF is not timing)
  • BOOL     Timer.TT              Timer Timing Bit, set when instruction is accumulating time.
  • BOOL     Timer.DN             Timer Done BIT, cleared when the accumulator reaches the preset.
  • DINT      Timer.PRE           Timer Preset , target value in milliseconds.
  • DINT      Timer.ACC           Timer accumulator, running value of timer in milliseconds.

Note: Timer must be scanned at a minimum of once every 69 minutes. A major fault will occur if the preset or accumulator fall below 0 (are negative). Slightly confusing instruction.